CPE 200: Digital Logic Design II
Section: 1001
| Course | Section | Credits | Instructor | Dates | Status | Call Number |
|---|---|---|---|---|---|---|
| CPE 200 | 1001 | 3 (3 max credits) | Jun. 9, 2025 to Jul. 11, 2025 | Open | 52591 |
Description
Sequential circuits, finite state machines (FSMs), and integer arithmetic circuits. Timing analysis. Programmable logic devices (PLDs). Hardware Description Language (HDL). Assembly language.Prerequisites
CPE 100 with a grade of C or +
Notes
This is an Internet class; refer to Canvas instructions at https://unlv.instructure.com.Summer Term registration policies are not the same as Spring and Fall. Failure to familiarize yourself with Summer Term registration policies and procedures may result in penalties. Courses must be dropped the business day prior to start date to avoid penalties. Visit the Summer Term website at summerterm.unlv.edu for complete registration and schedule information.
- Drop Deadlines:
100% Refund: 6/6/2025
50% Refund: 6/13/2025
Last Day to Drop: 6/27/2025
This data is for informational purposes only. Please see for a full catalog and more information.